The IBM eServer z990 floating-point unit

z990 floatingpoint unit G. Gerwig H. Wetter E. M. Schwarz J. Haess C. A. Krygowski B. M. Fleischer M. Kroener The floating-point unit (FPU) of the IBM z990 eServer is the first one in an IBM mainframe with a fused multiply-add dataflow. It also represents the first time that an SRT divide algorithm (named after Sweeney, Robertson, and Tocher, who independently proposed the algorithm) was used in an IBM mainframe. The FPU supports dual architectures: the zSeries hexadecimal floating-point architecture and the IEEE 754 binary floating-point architecture. Six floating-point formats— including short, long, and extended operands—are supported in hardware. The throughput of this FPU is one multiplyadd operation per cycle. The instructions are executed in five pipeline steps, and there are multiple provisions to avoid stalls in case of data dependencies. It is able to handle denormalized input operands and denormalized results without a stall (except for architectural program exceptions). It has a new extended-precision divide and square-root dataflow. This dataflow uses a radix-4 SRT algorithm (radix-2 for square root) and is able to handle divides and square-root operations in multiple floating-point and fixed-point formats. For fixedpoint divisions, a new mechanism improves the performance by using an algorithm with which the number of divide iterations depends on the effective number of quotient bits.